Description
Main Chip Parameters:
- Master chip model: XCZU67DR-FFVE1156-2-i
- Clock recommended maximum speed: PLL/MMCM recommended maximum 775M
- PS application processor model: four core Cortex-A53, main frequency of 1333M
- PS real time processor model: dual core Cortex-R5, main frequency of 533MHz
- DDR specification model: DDR4, model of MT40A256M16LY-075:E; PS side, 2GB capacity, 64 bit-width, 2400M; PL side, 1GB capacity, 32 bit-width, 2666M
- Logic unit: 489K
- Lookup table: 224K
- DSP unit multiplier: 1872
- Block Ram: 22.8M Byte
- Ultra Ram: 45M Byte
- GTY (32.5G): 8
- Component temperature range: -40 to 85℃
- Speed level: -2
- Chip level: industrial
RF-67DR-Lite functional interface description:
- Development board power supply: power supply through dedicated Type-C interface, 9-12V input, with PD 12V function
- Development board clock: 33.33M (PS), 100M (PL), 26M (PS GTR)/156.25M (GTY)
- Ethernet: gigabit RTL8211E, PS GEM3
- USB interface: USB3.0 SLAVE, support USB3.0 virtual network port
- DEBUG: onboard UART+JTAG (FTDI solution) support ARM and FPGA development
- Optical port: one QSFP28 100GE optic port, maximum speed rate of 28Gbps
- EEPROM: one FM24C02 EEPROM, connect to PS
- SD card slot: SD1 of PS, 2.0 interface, can be started (SD 2.0 support up to 32G)
- EMMC: SDO of PS, capacity of 16GByte (or larger)
- LED and button: power on or off/reset, PS/PL button/PL LED, power status indicator/DONE indicator, USB indicator, etc.
- Boot setting switch: one BOOT toggle switch for boot setting
- Onboard FLASH: 64M Bytes
- Heat dissipation interface: two 12V heat dissipation interface, GH1.25-3P terminal
- Expansion IO port: lead out 16 x 3.3V single-ended TTL; 2lane PS GTR, 4lane GTY, 60P BTB connector
RF Functional Interfaces Parameters:
- Normal ADC number: 8-channel 2.95SPS sampling rate channel, 14bit, front end is balun
- High performance ADC number: 2-channel 5.9GSPS sampling rate channel, 14bit, front end is operational amplifier
- DAC number: 8-channel DAC, maximum sampling rate of 10Gbps
- RF range: up to 7.125G
- SNR: ≥57dB at 900MHz (average battery than 56dB)
- Isolation degree: 10M - 7.125G full band better than -65dB
- Channel consistency: the measured average error at 1G frequency is within the range of 0.3db, which is lower than 0.5db
- RF connector: MMCX female socket, requires MMCX male connector, other interfaces require adapter cables
- RF coupling mode: AC coupling mode, reserved ADC VCOM output
- Impedance control: RFSOC to Balun differential 100 ohms, Balun to MMCX single ended 50 ohms
- Note: The 2-channel ADC front-end with a 5.9G sampling rate uses a 1.9G bandwidth operational amplifier with high linearity for analog acquisition; All 8 channels of 2.95G are balun, with a bandwidth of 10M-10G (exceeding specifications, with a maximum RF input of 7.125G for the chip)
Package Included:
- 1 x Development Board
- 2 x Type-C Data Cable
- 1 x Storage Case
- 1 x 12V/5A Power Adapter
- 8 x MMCX RF Cable
- Master chip model: XCZU67DR-FFVE1156-2-i
- Clock recommended maximum speed: PLL/MMCM recommended maximum 775M
- PS application processor model: four core Cortex-A53, main frequency of 1333M
- PS real time processor model: dual core Cortex-R5, main frequency of 533MHz
- DDR specification model: DDR4, model of MT40A256M16LY-075:E; PS side, 2GB capacity, 64 bit-width, 2400M; PL side, 1GB capacity, 32 bit-width, 2666M
- Logic unit: 489K
- Lookup table: 224K
- DSP unit multiplier: 1872
- Block Ram: 22.8M Byte
- Ultra Ram: 45M Byte
- GTY (32.5G): 8
- Component temperature range: -40 to 85℃
- Speed level: -2
- Chip level: industrial
RF-67DR-Lite functional interface description:
- Development board power supply: power supply through dedicated Type-C interface, 9-12V input, with PD 12V function
- Development board clock: 33.33M (PS), 100M (PL), 26M (PS GTR)/156.25M (GTY)
- Ethernet: gigabit RTL8211E, PS GEM3
- USB interface: USB3.0 SLAVE, support USB3.0 virtual network port
- DEBUG: onboard UART+JTAG (FTDI solution) support ARM and FPGA development
- Optical port: one QSFP28 100GE optic port, maximum speed rate of 28Gbps
- EEPROM: one FM24C02 EEPROM, connect to PS
- SD card slot: SD1 of PS, 2.0 interface, can be started (SD 2.0 support up to 32G)
- EMMC: SDO of PS, capacity of 16GByte (or larger)
- LED and button: power on or off/reset, PS/PL button/PL LED, power status indicator/DONE indicator, USB indicator, etc.
- Boot setting switch: one BOOT toggle switch for boot setting
- Onboard FLASH: 64M Bytes
- Heat dissipation interface: two 12V heat dissipation interface, GH1.25-3P terminal
- Expansion IO port: lead out 16 x 3.3V single-ended TTL; 2lane PS GTR, 4lane GTY, 60P BTB connector
RF Functional Interfaces Parameters:
- Normal ADC number: 8-channel 2.95SPS sampling rate channel, 14bit, front end is balun
- High performance ADC number: 2-channel 5.9GSPS sampling rate channel, 14bit, front end is operational amplifier
- DAC number: 8-channel DAC, maximum sampling rate of 10Gbps
- RF range: up to 7.125G
- SNR: ≥57dB at 900MHz (average battery than 56dB)
- Isolation degree: 10M - 7.125G full band better than -65dB
- Channel consistency: the measured average error at 1G frequency is within the range of 0.3db, which is lower than 0.5db
- RF connector: MMCX female socket, requires MMCX male connector, other interfaces require adapter cables
- RF coupling mode: AC coupling mode, reserved ADC VCOM output
- Impedance control: RFSOC to Balun differential 100 ohms, Balun to MMCX single ended 50 ohms
- Note: The 2-channel ADC front-end with a 5.9G sampling rate uses a 1.9G bandwidth operational amplifier with high linearity for analog acquisition; All 8 channels of 2.95G are balun, with a bandwidth of 10M-10G (exceeding specifications, with a maximum RF input of 7.125G for the chip)
Package Included:
- 1 x Development Board
- 2 x Type-C Data Cable
- 1 x Storage Case
- 1 x 12V/5A Power Adapter
- 8 x MMCX RF Cable
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Am Oct 15, 2026 hat der Verkäufer die folgenden Angaben hinzugefügt: