DATE - 1/23/2026
INVENTORY CODE - 23222923
QUANTITY - 1
ITEM DESCRIPTION/TITLE - Sun SparcStation 10 Model: 144 w/ Sun Microsystems 501-1845 ZX & 128GB ram READ
TESTING PROCEDURES/PARAMETERS - System was powered on and connected to via serial port. Onboard diagnostics reported that the system was working aside from the NVRAM being dead. New NVRam replacements can be purchased through Ebay so this listing was priced taking that repair in to consideration. Please review the diagnostic information below to fully understand the state of this system as we are not experts with these systems and cannot attest to any more accuracy than what you see in the diagnostic report.
*Due to the age of the plastic and the retention of the RAM the plastic arms that you push to help pop the RAM out may be broken/damaged. The RAM can still be installed and the system boots recognizing all the ram but this will cause the RAM to be more difficult to remove in the future.*
COSMETIC
CONDITION - Fair - NVRam is dead but all else appears working.
Power-ON Reset
SMCC SPARCstation 10/20 UP/MP POST version VRV3.45 (09/11/95)
CPU_#0 TI, STP1021APGA(2.x) 1Mb External cache
CPU_#1 ******* NOT installed *******
CPU_#2 ******* NOT installed *******
CPU_#3 ******* NOT installed *******
<<< CPU_00000000 on MBus Slot_00000000 >>> IS RUNNING (MID = 00000008)
$$$$$ WARNING : No Keyboard Detected! $$$$$
MMU ICACHE_TLB bit pattern Test
MMU ICACHE_TLB context flush Test
MMU ICACHE_TLB region flush Test
MMU ICACHE_TLB segment flush Test
MMU ICACHE_TLB page flush Test
MMU ICACHE_TLB entire flush Test
MMU DCACHE_TLB.RBO_LCK Test
MMU D_cached_level2_PTP_test
MMU I_cached_level2_PTP_test
MMU Cached_root_pointer_PTP0_test
MMU TLB_HIT Test
MMU TLB_MISS Test
MMU TLB_PROBE test
ENDIAN-ness Test with IU_registers
ENDIAN-ness Test with FPU_registers
MMU Context Table Reg Test
MMU Context Register Test
MMU TLB Bit Pattern Tests
MMU Flush Tests
D-Cache RAM Write/Read Test
D-Cache PTAG Write/Read Test
D-Cache STAG Write/Read Test
I-Cache RAM Write/Read Test
I-Cache PTAG Write/Read Test
I-Cache STAG Write/Read Test
I-Cache Flush Test
Cache Flashclear Test
MXCC Register Test
MXCC E-Cache Tag RAM Test
MXCC E-Cache Data RAM Test (1 MB E$ DATA RAM, MXCC_CSR=00000000)
MXCC Non-Cache Block Zero Test
MXCC Non-Cache Block Copy Test
MXCC Cacheable Block Read Test
MXCC Cacheable Block Write Test
EMC/SMC Control Regs Tests
ECC Multiple UE Test
ECC Multiple CE Test
ECC Multiple CE, UE Test
FPU Register File Test
FPU Misaligned Reg Pair Test
FPU Single-precision Tests
FPU Double-precision Tests
FPU SP Invalid CEXC Test
FPU SP Overflow CEXC Test
FPU SP Underflow CEXC Test
FPU SP Divide-by-0 CEXC Test
FPU SP Inexact CEXC Test
FPU SP Trap Priority > Test
FPU SP Trap Priority < Test
FPU SP UE Trap Priority Test
FPU DP Invalid CEXC Test
FPU DP Overflow CEXC Test
FPU DP Underflow CEXC Test
FPU DP Divide-by-0 CEXC Test
FPU DP Inexact CEXC Test
FPU DP Trap Priority > Test
FPU DP Trap Priority < Test
FPU DP UE Trap Priority Test
FPU DP CE Trap Priority Test
Memory Address Pattern Test
System Interrupt Regs Tests
PROC0 Interrupt Regs Tests
Soft Interrupts OFF Test
Soft Interrupts ON Test
PROC0 User Timer Test
PROC0 Counter/Timer Test
System Counter Test
MSI/MSBI Control Reg Tests
IOMMU CAM NTA Pattern Test
IOMMU TLB NTA Pattern Test
IOMMU CAM TLB Comparator Test
IOMMU TLB Flush Tests
DMA2/MACIO ID Register Test
DMA2/MACIO E_CSR Reg. Test
LANCE Address Port Tests
LANCE Data Port Tests
DMA2/MACIO D_CSR Reg. Test
DMA2/MACIO D_ADDR Reg. Test
DMA2/MACIO D_BCNT Reg. Test
DMA2/MACIO D_NADDR Reg. Test
ESP Registers Tests
DMA2/MACIO P_CSR Reg. Test
DMA2/MACIO P_ADDR Reg. Test
DMA2/MACIO P_BCNT Reg. Test
PPORT Registers Tests
DMA2/MACIO PPORT IO Lpbck Tst
DMA2/MACIO PPORT XFR Lbck Tst
TOD Registers Test
Available Memory 0x1d000000
Allocating SRMMU Context Table
Context Table allocated, Available Memory 0x1cfc0000
Setting SRMMU Context Register
Context Table allocated, Available Memory 0x1cfc0000
Setting SRMMU Context Table Pointer Register
RAMsize allocated, Available Memory 0x1cfb0000
Allocating SRMMU Level 1 Table
Level 1 Table allocated, Available Memory 0x1cfafc00
Mapping RAM 0xffef0000
RAM mapped, Available Memory 0x1cfafa00
Mapping ROM 0xffd00000
ROM mapped, Available Memory 0x1cfaf800
Mapping ROM 0x00000000
ROM mapped, Available Memory 0x1cfaf000
ttya initialized
Cpu #0 TI,TMS390Z55
Cpu #1 Nothing there
Cpu #2 Nothing there
Cpu #3 Nothing there
Probing Memory Bank #0 16 Megabytes of DRAM
Probing Memory Bank #1 16 Megabytes of DRAM
Probing Memory Bank #2 16 Megabytes of DRAM
Probing Memory Bank #3 16 Megabytes of DRAM
Probing Memory Bank #4 16 Megabytes of DRAM
Probing Memory Bank #5 16 Megabytes of DRAM
Probing Memory Bank #6 16 Megabytes of DRAM
Probing Memory Bank #7 16 Megabytes of DRAM
Starting real time clock...
Incorrect configuration checksum;
Setting NVRAM parameters to default values.
Setting diag-switch? NVRAM parameter to true
Probing /iommuf,e0000000/sbusf,e0001000 at f,0 espdma esp sd st ledma le SUNW,bpp SUNW,DBRIe mmcodec
Probing /iommuf,e0000000/sbusf,e0001000 at 0,0 Nothing there
Probing /iommuf,e0000000/sbusf,e0001000 at 1,0 Nothing there
Probing /iommuf,e0000000/sbusf,e0001000 at 2,0 Nothing there
Probing /iommuf,e0000000/sbusf,e0001000 at 3,0 SUNW,leo
Cpu #0 TI,TMS390Z55
Cpu #1 Nothing there
Cpu #2 Nothing there
Cpu #3 Nothing there
Probing Memory Bank #0 16 Megabytes of DRAM
Probing Memory Bank #1 16 Megabytes of DRAM
Probing Memory Bank #2 16 Megabytes of DRAM
Probing Memory Bank #3 16 Megabytes of DRAM
Probing Memory Bank #4 16 Megabytes of DRAM
Probing Memory Bank #5 16 Megabytes of DRAM
Probing Memory Bank #6 16 Megabytes of DRAM
Probing Memory Bank #7 16 Megabytes of DRAM
Starting real time clock...
Incorrect configuration checksum;
Setting NVRAM parameters to default values.
Setting diag-switch? NVRAM parameter to true
Probing /iommuf,e0000000/sbusf,e0001000 at f,0 espdma esp sd st ledma le SUNW,bpp SUNW,DBRIe mmcodec
Probing /iommuf,e0000000/sbusf,e0001000 at 0,0 Nothing there
Probing /iommuf,e0000000/sbusf,e0001000 at 1,0 Nothing there
Probing /iommuf,e0000000/sbusf,e0001000 at 2,0 Nothing there
Probing /iommuf,e0000000/sbusf,e0001000 at 3,0 SUNW,leo
SPARCstation 10 (1 X SuperSPARC-II), No Keyboard
ROM Rev. 2.25, 128 MB memory installed, Serial #11184810.
Ethernet address aa:aa:aa:aa:aa:aa, Host ID: aaaaaaaa.
The IDPROM contents are invalid
Boot device: /iommu/sbus/ledmaf,400010/lef,c00000 File and args:
Internal loopback test -- Did not receive expected loopback packet.
Can't open boot device
Type help for more information
ok test-all
Testing /memory0,0
Testing /obio/SUNW,fdtwo0,700000
Testing floppy disk system. A formatted disk should be in the drive.
Test succeeded.
Testing /obio/zs0,0
No Keyboard
Selftest failed. Return code = -1
Testing /obio/zs0,100000
!"#$%&'()*+,-./0123456789:;<=>?ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~Testing /iommuf,e0000000/sbusf,e0001000/SUNW,leo3,0
Testing Leo
Testing Leo Command, Draw and Cross Registers
Testing leo command registers
Testing leo draw registers
Testing leo cross registers
Testing Frame Buffer Memory
Will write values to the Frame Buffer
Then verify values written to the Frame Buffer
This will take about two minutes
Leo selftest passed
Testing /iommuf,e0000000/sbusf,e0001000/ledmaf,400010/lef,c00000
Using AUI Ethernet Interface
Lance register test -- succeeded.
Internal loopback test -- Did not receive expected loopback packet.
Using TP Ethernet Interface
Lance register test -- succeeded.
Internal loopback test -- Did not receive expected loopback packet.
Selftest failed. Return code = -1
Testing /iommuf,e0000000/sbusf,e0001000/espdmaf,400000/espf,800000
Dma register test -- succeeded.
Esp register test -- succeeded.
Dma read test -- succeeded.
Dma write test -- succeeded.
ok module-info
MBus : 40 MHz
SBus : 20 MHz
CPU#0 : 75 MHz SuperSPARC-II / SuperCache 3.1/3.3
SMCC SPARCstation 10/20 UP/MP POST version VRV3.45 (09/11/95)
CPU_#0 TI, STP1021APGA(2.x) 1Mb External cache
CPU_#1 ******* NOT installed *******
CPU_#2 ******* NOT installed *******
CPU_#3 ******* NOT installed *******
<<< CPU_00000000 on MBus Slot_00000000 >>> IS RUNNING (MID = 00000008)
$$$$$ WARNING : No Keyboard Detected! $$$$$
MMU ICACHE_TLB bit pattern Test
MMU ICACHE_TLB context flush Test
MMU ICACHE_TLB region flush Test
MMU ICACHE_TLB segment flush Test
MMU ICACHE_TLB page flush Test
MMU ICACHE_TLB entire flush Test
MMU DCACHE_TLB.RBO_LCK Test
MMU D_cached_level2_PTP_test
MMU I_cached_level2_PTP_test
MMU Cached_root_pointer_PTP0_test
MMU TLB_HIT Test
MMU TLB_MISS Test
MMU TLB_PROBE test
ENDIAN-ness Test with IU_registers
ENDIAN-ness Test with FPU_registers
MMU Context Table Reg Test
MMU Context Register Test
MMU TLB Bit Pattern Tests
MMU Flush Tests
D-Cache RAM Write/Read Test
D-Cache PTAG Write/Read Test
D-Cache STAG Write/Read Test
I-Cache RAM Write/Read Test
I-Cache PTAG Write/Read Test
I-Cache STAG Write/Read Test
I-Cache Flush Test
Cache Flashclear Test
MXCC Register Test
MXCC E-Cache Tag RAM Test
MXCC E-Cache Data RAM Test (1 MB E$ DATA RAM, MXCC_CSR=00000000)
MXCC Non-Cache Block Zero Test
MXCC Non-Cache Block Copy Test
MXCC Cacheable Block Read Test
MXCC Cacheable Block Write Test
EMC/SMC Control Regs Tests
ECC Multiple UE Test
ECC Multiple CE Test
ECC Multiple CE, UE Test
FPU Register File Test
FPU Misaligned Reg Pair Test
FPU Single-precision Tests
FPU Double-precision Tests
FPU SP Invalid CEXC Test
FPU SP Overflow CEXC Test
FPU SP Underflow CEXC Test
FPU SP Divide-by-0 CEXC Test
FPU SP Inexact CEXC Test
FPU SP Trap Priority > Test
FPU SP Trap Priority < Test
FPU SP UE Trap Priority Test
FPU DP Invalid CEXC Test
FPU DP Overflow CEXC Test
FPU DP Underflow CEXC Test
FPU DP Divide-by-0 CEXC Test
FPU DP Inexact CEXC Test
FPU DP Trap Priority > Test
FPU DP Trap Priority < Test
FPU DP UE Trap Priority Test
FPU DP CE Trap Priority Test
Memory Address Pattern Test
System Interrupt Regs Tests
PROC0 Interrupt Regs Tests
Soft Interrupts OFF Test
Soft Interrupts ON Test
PROC0 User Timer Test
PROC0 Counter/Timer Test
System Counter Test
MSI/MSBI Control Reg Tests
IOMMU CAM NTA Pattern Test
IOMMU TLB NTA Pattern Test
IOMMU CAM TLB Comparator Test
IOMMU TLB Flush Tests
DMA2/MACIO ID Register Test
DMA2/MACIO E_CSR Reg. Test
LANCE Address Port Tests
LANCE Data Port Tests
DMA2/MACIO D_CSR Reg. Test
DMA2/MACIO D_ADDR Reg. Test
DMA2/MACIO D_BCNT Reg. Test
DMA2/MACIO D_NADDR Reg. Test
ESP Registers Tests
DMA2/MACIO P_CSR Reg. Test
DMA2/MACIO P_ADDR Reg. Test
DMA2/MACIO P_BCNT Reg. Test
PPORT Registers Tests
DMA2/MACIO PPORT IO Lpbck Tst
DMA2/MACIO PPORT XFR Lbck Tst
TOD Registers Test
Available Memory 0x1d000000
Allocating SRMMU Context Table
Context Table allocated, Available Memory 0x1cfc0000
Setting SRMMU Context Register
Context Table allocated, Available Memory 0x1cfc0000
Setting SRMMU Context Table Pointer Register
RAMsize allocated, Available Memory 0x1cfb0000
Allocating SRMMU Level 1 Table
Level 1 Table allocated, Available Memory 0x1cfafc00
Mapping RAM 0xffef0000
RAM mapped, Available Memory 0x1cfafa00
Mapping ROM 0xffd00000
ROM mapped, Available Memory 0x1cfaf800
Mapping ROM 0x00000000
ROM mapped, Available Memory 0x1cfaf000
ttya initialized
Cpu #0 TI,TMS390Z55
Cpu #1 Nothing there
Cpu #2 Nothing there
Cpu #3 Nothing there
Probing Memory Bank #0 16 Megabytes of DRAM
Probing Memory Bank #1 16 Megabytes of DRAM
Probing Memory Bank #2 16 Megabytes of DRAM
Probing Memory Bank #3 16 Megabytes of DRAM
Probing Memory Bank #4 16 Megabytes of DRAM
Probing Memory Bank #5 16 Megabytes of DRAM
Probing Memory Bank #6 16 Megabytes of DRAM
Probing Memory Bank #7 16 Megabytes of DRAM
Starting real time clock...
Incorrect configuration checksum;
Setting NVRAM parameters to default values.
Setting diag-switch? NVRAM parameter to true
Probing /iommuf,e0000000/sbusf,e0001000 at f,0 espdma esp sd st ledma le SUNW,bpp SUNW,DBRIe mmcodec
Probing /iommuf,e0000000/sbusf,e0001000 at 0,0 Nothing there
Probing /iommuf,e0000000/sbusf,e0001000 at 1,0 Nothing there
Probing /iommuf,e0000000/sbusf,e0001000 at 2,0 Nothing there
Probing /iommuf,e0000000/sbusf,e0001000 at 3,0 SUNW,leo
Cpu #0 TI,TMS390Z55
Cpu #1 Nothing there
Cpu #2 Nothing there
Cpu #3 Nothing there
Probing Memory Bank #0 16 Megabytes of DRAM
Probing Memory Bank #1 16 Megabytes of DRAM
Probing Memory Bank #2 16 Megabytes of DRAM
Probing Memory Bank #3 16 Megabytes of DRAM
Probing Memory Bank #4 16 Megabytes of DRAM
Probing Memory Bank #5 16 Megabytes of DRAM
Probing Memory Bank #6 16 Megabytes of DRAM
Probing Memory Bank #7 16 Megabytes of DRAM
Starting real time clock...
Incorrect configuration checksum;
Setting NVRAM parameters to default values.
Setting diag-switch? NVRAM parameter to true
Probing /iommuf,e0000000/sbusf,e0001000 at f,0 espdma esp sd st ledma le SUNW,bpp SUNW,DBRIe mmcodec
Probing /iommuf,e0000000/sbusf,e0001000 at 0,0 Nothing there
Probing /iommuf,e0000000/sbusf,e0001000 at 1,0 Nothing there
Probing /iommuf,e0000000/sbusf,e0001000 at 2,0 Nothing there
Probing /iommuf,e0000000/sbusf,e0001000 at 3,0 SUNW,leo
SPARCstation 10 (1 X SuperSPARC-II), No Keyboard
ROM Rev. 2.25, 128 MB memory installed, Serial #11184810.
Ethernet address aa:aa:aa:aa:aa:aa, Host ID: aaaaaaaa.
The IDPROM contents are invalid
Boot device: /iommu/sbus/ledmaf,400010/lef,c00000 File and args:
Internal loopback test -- Did not receive expected loopback packet.
Can't open boot device
Type help for more information
ok test-all
Testing /memory0,0
Testing /obio/SUNW,fdtwo0,700000
Testing floppy disk system. A formatted disk should be in the drive.
Test succeeded.
Testing /obio/zs0,0
No Keyboard
Selftest failed. Return code = -1
Testing /obio/zs0,100000
!"#$%&'()*+,-./0123456789:;<=>?ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~Testing /iommuf,e0000000/sbusf,e0001000/SUNW,leo3,0
Testing Leo
Testing Leo Command, Draw and Cross Registers
Testing leo command registers
Testing leo draw registers
Testing leo cross registers
Testing Frame Buffer Memory
Will write values to the Frame Buffer
Then verify values written to the Frame Buffer
This will take about two minutes
Leo selftest passed
Testing /iommuf,e0000000/sbusf,e0001000/ledmaf,400010/lef,c00000
Using AUI Ethernet Interface
Lance register test -- succeeded.
Internal loopback test -- Did not receive expected loopback packet.
Using TP Ethernet Interface
Lance register test -- succeeded.
Internal loopback test -- Did not receive expected loopback packet.
Selftest failed. Return code = -1
Testing /iommuf,e0000000/sbusf,e0001000/espdmaf,400000/espf,800000
Dma register test -- succeeded.
Esp register test -- succeeded.
Dma read test -- succeeded.
Dma write test -- succeeded.
ok module-info
MBus : 40 MHz
SBus : 20 MHz
CPU#0 : 75 MHz SuperSPARC-II / SuperCache 3.1/3.3
Used Condition
Please examine the photos as they are part of the description.
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We make every effort to be accurate in our listings. If an Error was made contact us directly . We'll correct it to the best of our ability
We want it to be clear to buyers that all items are SOLD AS PICTURED
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