Unlock a rare slice of semiconductor history with this exceptional offering: a 6-inch (150 mm) silicon wafer from Performance Semiconductor Corporation, marked Model R3010, the MIPS Floating-Point Unit (FPU) companion to early MIPS CPU architectures. This wafer and comes from the era when chip design paved the way for modern high-performance computing.

  • Diameter: 6″ (150 mm) — large format wafer, ideal for display, educational use or lab exploration.

  • Model: R3010 (MIPS FPU unit) — an intriguing piece of semiconductor engineering heritage.

  • Condition: “Great condition – will reward careful inspection with magnifying glass or microscope.” 

  • Category: Vintage computing / rare collector’s semiconductor item. 

  • Quantity: Multiple available (more than 10) — but each is unique; these won’t last. 

  • Shipping from: North Point, Hong Kong — international shipping with import fees included. 

  • Returns: 30-day returns accepted (buyer pays return shipping).

  1. Collector’s Appeal: Semiconductor wafers from the R3010/MIPS era are rare. Whether you’re a vintage computing enthusiast, academic researcher, or display collector, this wafer makes an outstanding conversation piece and historical artifact.

  2. Visual & Educational Value: The wafer surface—with visible die, scribe lines, wafer edge, and wafer-map prints—offers a striking visual reminder of silicon-based innovation. Great for classroom demonstrations, maker labs, or tech-industry displays.

  3. Investment Potential: Items like this become increasingly scarce. Acquiring a recognized silicon wafer from a documented legacy architecture can be a smart long-term hold.


These wafers are in beautiful condition and will absolutly reward any viewer using a good magnifying glass or a simple microscope. Perfect for students and teachers or great as a display item in your den or office.

The wafers are clearly marked with the R3010 logo on a california License Plate. They have the MIPS and Performace Semiconductor logos.

The R3010 is the FPU for the MIPS R3000 CPU. It provides high-speed floating point capability for systems based on the R3000 CPU. The organization of the FPU architecture is similar to that of the R3000 CPU, and allows for optimization of both integer and floating-point performance.

The R3010 FPU connects seamlessly to the R3000 CPU via the R3000 coprocessor interface CP1, and since both units receive instructions in parallel, floating-point instructions can be initiated at the same single cycle rate as fixed-point instructions.

R3010 FPU can perform conversion, comparison, load, store, move and arithmetic operations with single and double-precision numbers. The R3010 FPU resides on the same system bus as the main CPU, and communicates with the CPU using R3000 co-processor interface. During its operation the R3010 co-processor monitors system bus, and when it encounters floating-point instruction it loads it into 6-stage pipeline, where the instruction is decoded and executed. For instruction execution the FPU utilizes three calculation units: Addition/Subtraction, Multiplication and Division. Operations in these units can be performed concurrently, which allows the co-processor to execute up to three different instructions at the same time. Also, during execution of floating-point instructions the main processor may continue to execute non-floating instructions. Once the FPU finishes instruction processing, it sends results and exception data back to the CPU. Please note that while the co-processor doesn't require assistance of the main CPU in processing floating-point instructions, it still requires the main CPU to generate necessary cache and memory signals.
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