MC68HC68T1 Real-time clock plus RAM with serial interface

 The MC68HC68T1 HCMOS Clock/RAM peripheral contains a real±time clock/calendar, a 32 x 8 static RAM, and a synchronous, serial, three±wire interface for communication with a microcontroller or processor. Operating in a burst mode, successive Clock/RAM locations can be read or written using only a single starting address. An on±chip oscillator allows acceptance of a selectable crystal frequency or the device can be programmed to accept a 50/60 Hz line input frequency. 

 The LINE and system voltage (VSYS) pins give the MC68HC68T1 the capability for sensing power±up/power±down conditions, a capability useful for battery±backup systems. The device has an interrupt output capable of signaling a microcontroller or processor of an alarm, periodic interrupt, or power sense condition. An alarm can be set for comparison with the seconds, minutes, and hours registers. This alarm can be used in conjunction with the power supply enable (PSE) output to initiate a system power±up sequence if the VSYS pin is powered to the proper level. 

 A software power±down sequence can be initiated by setting a bit in the interrupt control register. This applies a reset to the CPU via the CPUR pin, sets the clock out (CLKOUT) and PSE pins low, and disables the serial interface. This condition is held until a rising edge is sensed on the VSYS input pin, signaling system power coming on, or by activation of a previously enabled interrupt if the VSYS pin is powered up. 

 A watchdog circuit can be enabled that requires the microcontroller or processor to toggle the slave select (SS) pin of the MC68HC68T1 periodically without performing a serial transfer. If this condition is not met, the CPUR resets the CPU. line

 • Full Clock Features Ð Seconds, Minutes, Hours (AM/PM), Day±of±Week, Date, Month, Year (0 ± 99), Auto Leap Year

 • 32±Byte General Purpose RAM

 • Direct Interface to Motorola SPI and National MICROWIRE Serial Data Ports

 • Minimum Timekeeping Voltage: 2.2 V

 • Burst Mode for Reading/Writing Successive Addresses in Clock/RAM

 • Selectable Crystal or 50/60 Hz Line Input Frequency

 • Clock Registers Utilize BCD Data

 • Buffered Clock Output for Driving CPU Clock, Timer, Colon, or LCD Backplane

 • Power±On Reset with First Time±Up Bit

 • Freeze Circuit Eliminates Software Overhead During a Clock Read

 • Three Independent Interrupt Modes Ð Alarm, Periodic, or Power±Down

 • CPU Reset Output Ð Provides Orderly Power±Up/Power±Down

 • Watchdog Circuit • Pin±for±Pin Replacement for CDP68HC68T1

 • Chip Complexity: 8500 FETs or 2125 Equivalent Gates

 • Also See Application Notes ANE425 ªUse of the MC68HC68T1 RTC with M6805 Microprocessorº, AN457 ªProviding a Real±Time Clock for the MC68302º, and AN1065 ªUse of the MC68HC68T1 Real±Time Clock with Multiple Time Bases

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