| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Core(TM) i3-6100 CPU @ 3.70GHz |
| Cores: | 2 |
| Logical processors: | 4 |
| Base frequency: | 3700 MHz |
| Bus / reference frequency: | 100 MHz |
| Processor type: | Original OEM Processor |
| CPUID signature: | 506E3 |
| Family: | 6 (06h) |
| Model: | 94 (05Eh) |
| Stepping: | 3 (03h) |
| TLB/Cache details: | 64-byte Prefetching Data TLB: 1-GB pages, 4-way set associative, 4 entries Data TLB: 4-KB Pages, 4-way set associative, 64 entries Instruction TLB: 4-KByte pages, 8-way set associative, 64 entries L2 TLB: 1-MB, 4-way set associative, 64-byte line size Shared 2nd-Level TLB: 4-KB / 2-MB pages, 6-way associative, 1536 entries. Plus, 1-GB pages, 4-way, 16 entries |
| Cache: | L1 data | L1 instruction | L2 | L3 |
|---|---|---|---|---|
| Size: | 2 x 32 KB | 2 x 32 KB | 2 x 256 KB | 3 MB |
| Associativity: | 8-way set associative |
8-way set associative |
4-way set associative |
12-way set associative |
| Line size: | 64 bytes | 64 bytes | 64 bytes | 64 bytes |
| Comments: | Direct-mapped | Direct-mapped | Non-inclusive Direct-mapped |
Inclusive Shared between all cores |
| Instruction set extensions | Additional instructions | ||
|---|---|---|---|
| MMX | ADCX/ADOX instructions | ||
| SSE | Advanced Bit manipulation | ||
| SSE2 | CLFLUSH | ||
| SSE3 | CLFLUSHOPT | ||
| SSSE3 | CMOV | ||
| SSE4.1 | CMPXCHG16B | ||
| SSE4.2 | CMPXCHG8B | ||
| AES | Enhanced REP MOVSB/STOSB | ||
| AVX | FXSAVE/FXRSTORE | ||
| AVX2 | INVPCID | ||
| BMI1 | MONITOR/MWAIT | ||
| BMI2 | MOVBE | ||
| F16C | PCLMULDQ | ||
| FMA | POPCNT | ||
| Memory Protection Extensions (MPX) | PREFETCH/PREFETCHW | ||
| Supervisor-Mode Access Prevention and CLAC / STAC instructions | RD/WR FSGSBASE instructions | ||
| Supervisor Mode Execution Protection | RDRAND | ||
| Software Guard Extensions (SGX) | RDSEED | ||
| RDTSCP | |||
| SYSENTER/SYSEXIT | |||
| XSAVE/XRESTORE states | |||
| XSETBV/XGETBV are enabled |
| Major features | Other features | ||
|---|---|---|---|
| On-chip Floating Point Unit | 1 GB large page support | ||
| 64-bit / Intel 64 | 36-bit page-size extensions | ||
| NX bit/XD-bit | 64-bit debug store | ||
| Hyper-Threading Technology | Advanced programmable interrupt controller | ||
| Intel Virtualization | CPL qualified debug store | ||
| Enhanced SpeedStep | Clock modulation duty cycle extension | ||
| Debug store | |||
| Debugging extensions | |||
| Digital Thermal Sensor capability | |||
| Extended xAPIC support | |||
| Intel Processor Trace | |||
| LAHF/SAHF support in 64-bit mode | |||
| Machine check architecture | |||
| Machine check exception | |||
| Memory-type range registers | |||
| Model-specific registers | |||
| Package thermal management | |||
| Page attribute table | |||
| Page global extension | |||
| Page-size extensions (4MB pages) | |||
| Pending break enable | |||
| Perfmon and Debug capability | |||
| Physical address extensions | |||
| Power Limit Notification capability | |||
| Process context identifiers | |||
| Self-snoop | |||
| TSC rate is ensured to be invariant across all states | |||
| Thermal monitor | |||
| Thermal monitor 2 | |||
| Thermal monitor and software controlled clock facilities | |||
| Time stamp counter | |||
| Timestamp counter deadline | |||
| Virtual 8086-mode enhancements | |||
| xTPR Update Control |